| CPC H04L 27/2647 (2013.01) [H04L 5/001 (2013.01)] | 20 Claims |
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1. An apparatus comprising:
at least one processor, and
at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to:
receive a first transmission from an antenna, via a first frontend circuitry, the first transmission comprising a first carrier including a first signal and a second carrier including a second signal, wherein the first and second carriers are separated in frequency within a first operational band;
split the first transmission into a first channel and a second channel;
downconvert the first channel to centre the first carrier at a baseband frequency to extract the first signal;
downconvert the second channel to centre the second carrier at the baseband frequency to extract the second signal; and
provide the first signal to a first processor and the second signal to a second processor,
wherein the first and second processors are associated with first and second subscriber identity modules respectively, and
wherein the first front end circuitry is configured to operate at a third generation partnership project (3GPP) lowband frequency range, and comprises a plurality of paths each configured to operate within one or more bandgroup(s).
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