| CPC H04L 25/4917 (2013.01) [H04B 1/40 (2013.01); H04L 27/22 (2013.01); H03M 1/1245 (2013.01)] | 6 Claims |
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1. A signal generation apparatus comprising:
a parallel data output unit that outputs parallel data of a plurality of bits;
a plurality of transceivers that have a first-in first-out (FIFO) for storing parallel data of N bits among the parallel data of the plurality of bits output from the parallel data output unit, and convert the parallel data of N bits stored in the FIFO into serial data of 1 bit;
a phase synchronization control unit that controls a phase of the serial data of 1 bit converted by each of the transceivers;
a division clock output unit that outputs a division clock obtained by dividing a frequency of an external clock;
a division ratio setting unit that sets a division ratio of the division clock in the division clock output unit;
a clock selection unit that selects any one of the external clock and the division clock;
a rate control unit that performs control of outputting a toggle pattern having a frequency half a frequency of the division clock or the external clock selected by the clock selection unit as the serial data of 1 bit from each of the transceivers; and
a phase demodulation unit that measures a voltage value corresponding difference between the division clock or the external clock selected by the clock selection unit and the toggle pattern,
wherein the phase synchronization control unit includes
a phase acquisition processing unit that executes a phase acquisition process of acquiring the voltage value measured by the phase demodulation unit while changing a phase of the toggle pattern from an initial value,
a phase difference calculation processing unit that executes a phase difference calculation process of calculating an initial phase difference between the division clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern, based on a relationship between the voltage value acquired by the phase acquisition processing unit and a change amount from the initial value of the phase of the toggle pattern, and
a phase shift processing unit that executes a phase shift process of moving the phase of the toggle pattern from the initial value by the initial phase difference such that a phase difference between the division clock or the external clock selected by the clock selection unit and the toggle pattern is within a predetermined range,
the phase synchronization control unit repeatedly executes the phase acquisition process, the phase difference calculation process, and the phase shift process while causing the division ratio setting unit to gradually decrease the division ratio, and
the clock selection unit selects the external clock instead of the division clock after the phase acquisition process, the phase difference calculation process, and the phase shift process are executed when the division ratio is a predetermined minimum value.
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