US 12,438,694 B2
Triplication-based fault attack countermeasure
Florian Reneld Ghislain Caullery, Cannes (FR); Frederic Amiel, Nice (FR); and Nicolas Thaddee Courtois, Mougins (FR)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jul. 17, 2023, as Appl. No. 18/353,761.
Prior Publication US 2025/0030535 A1, Jan. 23, 2025
Int. Cl. H04L 9/00 (2022.01)
CPC H04L 9/004 (2013.01) 31 Claims
OG exemplary drawing
 
1. An apparatus for secure processing, comprising:
a memory system comprising instructions; and
a processor system coupled to the memory system, wherein the processor system is configured to:
provide an input value to a circuit that generates a first output value;
obtain a tweak value;
obtain a plurality of first intermediate output values, wherein the plurality of first intermediate output values are generated by the circuit based on a function of the input value and the tweak value;
embed the plurality of first intermediate output values into a structure;
obtain a plurality of second intermediate output values, wherein the plurality of second intermediate output values are a function of the plurality of first intermediate output values, a random number, and an inverse of the tweak value;
determine a most common value of the plurality of second intermediate output values, wherein the most common value represents a fault injection resistant value or a random value;
obtain a third intermediate value, the third intermediate value based on a function of the most common value and an inverse of the random number;
project the third intermediate value from the structure to obtain a second output value; and
output the second output value.