| CPC H04L 7/0033 (2013.01) | 21 Claims |
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1. A locked-loop circuit comprising:
a variable delay line comprising a plurality of delay elements;
a phase detector configured to determine any phase difference between a reference clock signal and an output clock signal output from the variable delay line; and
a delay controller configured to control at least one delay setting to control a delay of the variable delay line;
wherein the locked-loop circuit is operable in a delay-locked-loop mode in which said reference clock signal is input to the variable delay line and the delay controller is configured to control said delay setting based on an output of the phase detector to achieve phase lock between the reference signal and the output signal;
wherein the locked loop circuit is operable in a frequency-locked-loop mode in which at least part of variable delay line is configured to be operated as a controlled oscillator to provide an oscillator signal, a frequency monitor is configured to determine a frequency relationship between the reference clock signal and the oscillator signal and the delay controller is configured to control said delay setting based on an output of the frequency monitor so as achieve a predetermined frequency relationship between the reference clock signal and the oscillator signal which corresponds to the delay of the variable delay line being a desired delay value; and
wherein the locked-loop circuit is configured to operate in the frequency-locked-loop mode for a first period and then transition to operating in the delay-locked-loop mode, wherein the delay setting at the end of the first period of operation in the frequency-locked-loop mode is used as the delay setting at the start of the operation in the delay-locked-loop mode.
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