US 12,438,557 B2
Parallelized decoding of variable-length prefix codes
Daniel Lo, Bothell, WA (US); and Blake D. Pelton, Redmond, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Appl. No. 18/034,832
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
PCT Filed Jul. 27, 2021, PCT No. PCT/US2021/043258
§ 371(c)(1), (2) Date May 1, 2023,
PCT Pub. No. WO2022/093343, PCT Pub. Date May 5, 2022.
Application 18/034,832 is a continuation of application No. 17/084,169, filed on Oct. 29, 2020, granted, now 11,211,945, issued on Dec. 8, 2021.
Prior Publication US 2023/0403028 A1, Dec. 14, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 7/40 (2006.01); H03M 7/30 (2006.01)
CPC H03M 7/6023 (2013.01) [H03M 7/40 (2013.01); H03M 7/6005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system for decoding variable-length codes in a parallel process, the system comprising:
at least one processor;
memory in electronic communication with the at least one processor; and
instructions stored in the memory, the instructions being executable by the at least one processor to:
divide a stream of variable-length code words received as a concatenated bit stream into a series of fixed-length words, each of the fixed-length words comprising at least a portion of an encoded symbol;
receive, at a first set of decoder circuits, a first fixed-length word and a first prior fixed-length word from the series of fixed-length words, each decoder circuit of the first set of decoder circuits has a respective fixed leftover bit count;
generate, for each decoder circuit of the first set of decoder circuits, a respective output comprising a decoding result and a new leftover bit-count, each respective output determined based on the first fixed-length word, the first prior fixed-length word, and the respective fixed leftover bit-count;
generate a set of selected decoder circuit outputs by selecting outputs of the first set of decoder circuits based on a set of first leftover bit-counts of a second set of decoder circuits;
select one decoder circuit output of the set of selected decoder circuit outputs based on a second leftover bit-count of a third set of decoder circuits; and
output the decoding result and the new leftover bit-count corresponding to the selected one decoder circuit output.