US 12,438,553 B2
Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors
Gautham Chinya, Sunnyvale, CA (US); Debabrata Mohapatra, San Jose, CA (US); Arnab Raha, San Jose, CA (US); Huichu Liu, Santa Clara, CA (US); and Cormac Brick, San Francisco, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 12, 2023, as Appl. No. 18/465,495.
Application 18/465,495 is a continuation of application No. 16/832,804, filed on Mar. 27, 2020, granted, now 11,804,851.
Prior Publication US 2024/0022259 A1, Jan. 18, 2024
Int. Cl. H03M 7/30 (2006.01); G06F 16/22 (2019.01); G06N 3/063 (2023.01); G06N 3/04 (2023.01); G06N 3/08 (2023.01)
CPC H03M 7/3082 (2013.01) [G06F 16/2237 (2019.01); G06N 3/063 (2013.01); G06N 3/04 (2013.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for performing a multiply-accumulate (MAC) operation, the apparatus comprising:
a memory to:
store a compressed tensor, the compressed tensor comprising one or more nonzero-valued elements in a tensor associated with the MAC operation, the tensor associated with the MAC operation further comprises one or more zero-valued elements, and
store a sparsity bitmap, the sparsity bitmap encoding one or more positions of the one or more nonzero-valued elements in the tensor associated with the MAC operation;
a processing element to perform the MAC operation using a nonzero-valued element stored in the memory; and
a multiplexer associated with the processing element, the multiplexer to:
receive a signal generated based on the sparsity bitmap,
select, based on the signal, the nonzero-valued element from the one or more non-zero elements, and
transmit the nonzero-valued element from the memory to the processing element.