US 12,438,550 B2
Continuous time signal processing systems and subsystems
Patrick W. Jungwirth, Bel Air, MD (US); and W. Michael Crowe, Madison, AL (US)
Assigned to The United States of America as represented by the Secretary of the Army, Washington, DC (US)
Filed by U.S. Army DEVCOM, Army Research Laboratory, Adelphi, MD (US)
Filed on Mar. 31, 2023, as Appl. No. 18/129,114.
Claims priority of provisional application 63/353,038, filed on Jun. 17, 2022.
Prior Publication US 2023/0412185 A1, Dec. 21, 2023
Int. Cl. H03M 1/38 (2006.01); H03M 1/12 (2006.01)
CPC H03M 1/125 (2013.01) [H03M 1/122 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A signal processing subsystem for processing an input signal having a measurement quantity, the signal processing subsystem comprising:
a plurality of N stages, where N≥2, each stage n (for 1≤n≤N) being configured to receive the input signal and corresponding reference levels for the measurement quantity, and to output an output code based on comparison between the input signal and reference levels;
a summing circuit configured to sum together the output codes from every stage n to provide a digital output code that approximates the measurement quantity of the input signal;
an amplifier circuit for the last stage, the amplifier circuit configured to receive the error voltage from the preceding stage, scale up the error voltage by a factor of MN-1, and output the scaled-up error voltage;
wherein each of the corresponding plurality of reference voltage levels received by the last stage is supplied to a first input of a corresponding comparator of the last stage, and the scaled-up error voltage is supplied to a second input of each comparator of the last stage;
a code converter circuit that receives the outputs of the comparators and converts them into the output code for the last stage, the output code coding for one of (a) a factor of 1/MN-1 multiplied by the highest reference level that does not exceed the scaled-up error voltage, or (b) a factor of 1/MN-1 multiplied by the nearest reference level to the scaled-up error voltage, wherein rounding is performed if the error voltage is equidistant between two reference levels.