| CPC H03L 7/0992 (2013.01) [H03L 7/093 (2013.01)] | 19 Claims |
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1. A system, comprising:
a primary Phase Locked Loop (PLL) circuit configured to receive a periodic reference signal at a first frequency and to output a first periodic signal at a second frequency, the primary PLL circuit comprising a primary Voltage Controlled Oscillator, (VCO) circuit configured to output the first periodic signal at the second frequency dependent on a first VCO control signal generated in the primary PLL and applied at a first VCO input of the primary VCO circuit;
a plurality of secondary PLL circuits, each configured to receive a divided periodic signal from the primary PLL circuit, and to output a respective periodic signal at the second frequency, each secondary PLL circuit comprising a respective secondary VCO circuit configured to output the respective periodic signal at the second frequency dependent on the first VCO control signal applied at a first VCO input of the secondary VCO circuit and a second VCO control signal generated in the secondary PLL and applied at a second VCO input of the secondary VCO circuit;
wherein at least one secondary PLL circuit is further configured to output a correction current;
a correction loop filter circuit configured to receive a combined correction current comprising a sum of correction currents from one or more secondary PLL circuits, and output a third VCO control signal to a second VCO input of the primary PLL circuit;
wherein the primary VCO circuit is further configured to output the first periodic signal dependent on the third VCO control signal.
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