US 12,438,547 B2
Phase-locked loop update cancellation
John Borkenhagen, Rochester, MN (US); Christopher Steffen, Rochester, MN (US); Grant P. Kesselring, Rochester, MN (US); and James Strom, Rochester, MN (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Oct. 23, 2023, as Appl. No. 18/492,453.
Prior Publication US 2025/0132763 A1, Apr. 24, 2025
Int. Cl. H03L 7/089 (2006.01)
CPC H03L 7/0891 (2013.01) 14 Claims
OG exemplary drawing
 
1. A phase-locked loop pulse cancelation method, the method comprising:
receiving, from a phase frequency detector of a phase-locked loop (PLL) at a pulse limiter circuit of the PLL, a first input pulse and a second input pulse, wherein pulse widths of the first and second input pulses indicate whether a reference clock signal of the PLL leads or lags a feedback clock signal of the PLL;
delaying the first and second input pulses by the selected duration to obtain a delayed first input pulse and a delayed second input pulse;
determining, by the pulse limiter circuit, whether a pulse width of the first input pulse or a pulse width of the second input pulse is greater than a selected duration by logically ANDing the first input pulse with the delayed first input pulse and logically ANDing the second input pulse with the delayed second input pulse;
based on determining the pulse width of the first input pulse or the pulse width of the second input pulse is greater than the selected duration:
setting, by the pulse limiter circuit, a pulse width of a first output pulse equal to a pulse width of a second output pulse width; and
sending, by the pulse limiter circuit, the first and second output pulses to a charge pump of the PLL, such that no phase adjustment to the feedback clock signal is made based on the first and second input pulses.