US 12,438,546 B1
Driver/inverter using lower voltage tolerant devices
Sri Ram Kumar Jayanthi, Andhra Pradesh (IN); Akhil Thotli, Andhra Pradesh (IN); and Rahul Gupta, Haryana (IN)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Jun. 13, 2023, as Appl. No. 18/209,203.
Int. Cl. H03K 19/0944 (2006.01)
CPC H03K 19/0944 (2013.01) 8 Claims
OG exemplary drawing
 
1. A logic circuit comprising:
a first cascode circuit comprising:
a first transistor, a second transistor, and a third transistor connected in series, the third transistor connected to an output of the first cascode circuit; and
a first diode connected in parallel with the third transistor; and
a second cascode circuit comprising:
a fourth transistor, a fifth transistor, and a sixth transistor connected in series, the sixth transistor connected to an output of the second cascode circuit; and
a second diode connected in parallel with the sixth transistor,
wherein the output of the first cascode circuit is connected to the output of the second cascode circuit and connects the first cascode circuit in series with the second cascode circuit.