US 12,438,542 B2
Wide frequency range high speed clock multiplexer
Hyung-Joon Jeon, Irvine, CA (US); Jun Cao, Irvine, CA (US); Seong Ho Lee, Aliso Viejo, CA (US); and Anand J Vasani, Irvine, CA (US)
Assigned to Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed by Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed on Apr. 28, 2023, as Appl. No. 18/141,344.
Prior Publication US 2024/0364334 A1, Oct. 31, 2024
Int. Cl. H03K 17/693 (2006.01)
CPC H03K 17/693 (2013.01) 17 Claims
OG exemplary drawing
 
1. A device, receiving an input signal and providing an output signal, the device comprising:
a first circuit receiving an input signal having a first frequency, the first circuit including a first node and a second node;
a second circuit receiving an input signal having a second frequency different from the first frequency, the second circuit including a first node and a second node; a first inductor coupled between the first node of the first circuit and the first node of the second circuit;
a second inductor coupled between the second node of the first circuit and the second node of the second circuit; and
a first transistor between the first node of the second circuit and the second node of the second circuit operating as a first switch that, upon activation responsive to a control signal corresponding to a high-speed path, operates in a closed state to electrically couple the first node of the second circuit and the second node of the second circuit, the first transistor coupled to a plurality of transistors that are electrically coupled between a power source and a drain or source node of the first transistor and operate in the closed state with the first transistor in the high-speed path.