US 12,438,541 B2
Low voltage can transceiver
Amit Patil, Hubli (IN); Deep Banerjee, Bangalore (IN); Lokesh Kumar Gupta, Bangalore (IN); Viswanathan Venkatesh Kumar, Bangaluru (IN); Upasana Bhattacharya, Bangalore (IN); and Pallabi Pramanik, Singur (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 30, 2023, as Appl. No. 18/344,990.
Prior Publication US 2025/0007513 A1, Jan. 2, 2025
Int. Cl. H03K 17/687 (2006.01); H04L 12/40 (2006.01)
CPC H03K 17/6871 (2013.01) [H04L 12/40032 (2013.01); H04L 2012/40215 (2013.01); H04L 2012/40273 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first transistor having a drain, a control terminal, and a source coupled to a voltage supply terminal;
a second transistor having a source, a control terminal, and a drain coupled to the drain of the first transistor;
a third transistor having a control terminal, having a drain coupled to the control terminal of the second transistor, and having a source coupled to a the source of the second transistor; and
a fourth transistor having a control terminal and a source coupled to the source of the second transistor, wherein the third transistor is configured to inactivate the second transistor when a voltage at a drain of the fourth transistor is above a threshold.