| CPC H03K 5/1565 (2013.01) [H03K 5/00006 (2013.01); H03K 19/17784 (2013.01)] | 20 Claims |
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1. A clock doubler comprising:
a first differential gate configured to receive a first clock signal and a first complementary clock signal through a first differential input terminal of the first differential gate and receive a second clock signal and a second complementary clock signal through a second differential input terminal of the first differential gate to generate an output clock signal and configured to adjust a duty cycle of the output clock signal based on a first bias control signal; and
a second differential gate configured to receive the second clock signal and the second complementary clock signal through a first differential input terminal of the second differential gate and receive the first clock signal and the first complementary clock signal through a second differential input terminal of the second differential gate to generate a complementary output clock signal and configured to adjust a duty cycle of the complementary output clock signal based on a second bias control signal,
wherein a value of the second bias control signal is changed independently a value of the first bias control signal.
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