US 12,438,532 B2
Power saving circuits to adjust frequency according to dynamic timing margin changes and adjust supply voltage to restore desired frequency and related methods
Darshan Kumar Nandanwar, Bangalore (IN); Siddesh Halavarthi Math Revana, Bangalore (IN); Kuldeep Singh Chahal, Noida (IN); Srinivasa Kumar Munivenkata Gowda, Bangalore (IN); and Nilesh Dhavlikar, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 4, 2024, as Appl. No. 18/594,916.
Prior Publication US 2025/0279772 A1, Sep. 4, 2025
Int. Cl. H03K 5/135 (2006.01); G06F 1/10 (2006.01)
CPC H03K 5/135 (2013.01) [G06F 1/10 (2013.01)] 27 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising a first clock domain comprising:
a first processing circuit comprising:
a first critical signal path having a first propagation delay based on a supply voltage provided to the first clock domain, wherein the first critical signal path is one of a plurality of critical signal paths that limit a frequency of a clock signal provided to the first clock domain; and
a margin management circuit comprising:
a configurable logic circuit comprising a first delay path having a first configurable delay corresponding to the first propagation delay;
an edge detector circuit configured to detect a first timing margin of the first delay path, the first timing margin based on a time difference between the first configurable delay and a period of the clock signal; and
a frequency adjustment circuit configured to generate a first frequency adjustment signal to adjust the frequency of the clock signal based on the first timing margin.