US 12,438,529 B2
Oscillation circuit
Kazuki Miyao, Kawasaki Kanagawa (JP); Tomoharu Kambashi, Hiratsuka Kanagawa (JP); and Hiroshi Yoshino, Yokohama Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on May 17, 2024, as Appl. No. 18/667,927.
Claims priority of application No. 2023-158937 (JP), filed on Sep. 22, 2023.
Prior Publication US 2025/0105827 A1, Mar. 27, 2025
Int. Cl. H03K 3/03 (2006.01); H03K 5/04 (2006.01)
CPC H03K 3/0315 (2013.01) [H03K 5/04 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An oscillation circuit comprising:
a ring oscillator;
a first transistor having a gate terminal coupled to an output port of the ring oscillator and a drain terminal coupled to a first node;
a second transistor having a drain terminal and a gate terminal that are both coupled to the first node;
a third transistor having a gate terminal coupled to the first node and a drain terminal coupled to a second node;
a fourth transistor having a gate terminal coupled to the first node and a drain terminal coupled to a third node;
a fifth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node; and
a voltage buffer having an input port coupled to the second node.