US 12,438,528 B2
Transistor DV/DT control circuit
Hongwei Jia, Aliso Viejo, CA (US); Santosh Sharma, Austin, TX (US); Daniel M. Kinzer, El Segundo, CA (US); Victor Sinow, Fresno, CA (US); and Matthew Anthony Topp, Colorado Springs, CO (US)
Assigned to Navitas Semiconductor Limited, Dublin (IE)
Filed by NAVITAS SEMICONDUCTOR LIMITED, Dublin (IE)
Filed on Nov. 17, 2023, as Appl. No. 18/513,456.
Application 18/513,456 is a continuation of application No. 17/853,740, filed on Jun. 29, 2022, granted, now 11,855,635.
Claims priority of provisional application 63/202,940, filed on Jun. 30, 2021.
Claims priority of application No. 202110732707.1 (CN), filed on Jun. 30, 2021.
Prior Publication US 2024/0235531 A1, Jul. 11, 2024
Int. Cl. H03K 3/012 (2006.01)
CPC H03K 3/012 (2013.01) 18 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first switch having a first gate terminal, a first source terminal and a first drain terminal;
a sense circuit coupled to the first drain terminal and arranged to generate a signal in response to sensing a voltage at the first drain terminal; and
a control circuit coupled to the first gate terminal and arranged to change a voltage at the first gate terminal in response to receiving the signal, wherein the voltage at the first gate terminal is changed at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage,
wherein the second intermediate voltage is lower than the first intermediate voltage; and
wherein the voltage at the first gate terminal is further changed from the second intermediate voltage to an off-state voltage at a third rate of voltage with respect to time, and wherein the first rate of voltage with respect to time is higher than the second rate of voltage with respect to time.