| CPC H03H 7/0115 (2013.01) [H03H 7/1758 (2013.01); H03H 7/1775 (2013.01); H03H 7/46 (2013.01); H03H 7/463 (2013.01); H03H 2001/0085 (2013.01)] | 7 Claims |
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1. A multilayer electronic component comprising:
an input terminal;
a plurality of output terminals;
a plurality of parallel resonant circuits;
a plurality of serial resonant circuits;
a stack including a plurality of dielectric layers stacked together, a plurality of first conductors, and a plurality of second conductors;
a first inductor;
a second inductor; and
a third inductor, wherein
the first inductor and the third inductor are included in one of the plurality of parallel resonant circuits or the plurality of serial resonant circuits,
the second inductor is included in the other of the plurality of parallel resonant circuits or the plurality of serial resonant circuits;
the plurality of first conductors constitute the one of the plurality of parallel resonant circuits or the plurality of serial resonant circuits, and does not constitute the other of the plurality of parallel resonant circuits or the plurality of serial resonant circuits,
the plurality of second conductors constitute the other of the plurality of parallel resonant circuits or the plurality of serial resonant circuits, and does not constitute the one of the plurality of parallel resonant circuits or the plurality of serial resonant circuits,
the plurality of first conductors include a first conductor group,
the plurality of second conductors include a second conductor group arranged in a region adjacent to a region where the first conductor group is arranged,
the plurality of first conductors further include a third conductor group arranged in a region adjacent to the region where the second conductor group is arranged and located to sandwich, with the region where the first conductor group is arranged, the region where the second conductor group is arranged,
the plurality of output terminals include a first terminal, a second terminal, and a third terminal,
the first conductor group includes a first conductor layer constituting the first inductor, and constitutes at least part of a circuit provided on a path connecting the input terminal and the first terminal,
the second conductor group includes a second conductor layer constituting the second inductor, and constitutes at least part of a circuit provided on a path connecting the input terminal and the second terminal,
the third conductor group includes a third conductor layer constituting the third inductor, and constitutes at least part of a circuit provided on a path connecting the input terminal and the third terminal,
the stack includes a bottom surface that is located at a lower end in a stacking direction of the plurality of dielectric layers, a top surface that is located at an upper end in the stacking direction of the plurality of dielectric layers, and a first side surface, a second side surface, a third side surface, and a fourth side surface connecting the bottom surface and the top surface,
the first side surface and the second side surface are opposite to each other,
the third side surface and the fourth side surface are opposite to each other, and
all of the first conductor layer, the second conductor layer, and the third conductor layer are arranged at positions closer to the second side surface than to the first side surface.
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