US 12,438,136 B2
Semiconductor apparatus and method for manufacturing the same
Meili Wang, Beijing (CN); Xuan Liang, Beijing (CN); Fei Wang, Beijing (CN); Lei Wang, Beijing (CN); Yafeng Yang, Beijing (CN); Xue Dong, Beijing (CN); Zhanfeng Cao, Beijing (CN); Mingxing Wang, Beijing (CN); Fuqiang Li, Beijing (CN); Chenyang Zhang, Beijing (CN); Xinxin Zhao, Beijing (CN); Yanling Han, Beijing (CN); Lei Wang, Beijing (CN); Xuan Feng, Beijing (CN); and Yapeng Li, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Nov. 29, 2021, as Appl. No. 17/536,268.
Claims priority of application No. 202110273811.9 (CN), filed on Mar. 12, 2021.
Prior Publication US 2022/0293576 A1, Sep. 15, 2022
Int. Cl. H01L 25/16 (2023.01); H01L 21/66 (2006.01); H10F 39/00 (2025.01); H10H 20/857 (2025.01); H10H 20/01 (2025.01)
CPC H01L 25/167 (2013.01) [H01L 22/20 (2013.01); H10F 39/811 (2025.01); H10H 20/857 (2025.01); H10F 39/011 (2025.01); H10H 20/0364 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor apparatus, comprising:
a base substrate;
a chip arranged on the base substrate, wherein the chip comprises a chip main body and a plurality of terminals arranged on the chip main body;
a terminal expansion layer arranged on the base substrate, wherein the terminal expansion layer comprises a conductive material, and the terminal expansion layer and at least one terminal are located on a same side of the chip main body; and
a plurality of expansion wires in the terminal expansion layer, wherein the plurality of expansion wires are electrically connected to the plurality of terminals, respectively, so as to lead out the plurality of terminals,
wherein an orthographic projection of at least one expansion wire on the base substrate completely covers an orthographic projection of a terminal electrically connected to the expansion wire on the base substrate,
wherein the chip comprises a first chip, a second chip, and a third chip, the first chip, the second chip, and the third chip being configured to implement different functions from each other,
wherein the first chip comprises at least two first terminals, and the second chip comprises at least two second terminals,
wherein the first chip comprises at least one of a light-emitting chip and a sensor chip, and the second chip comprises at least one of a sensor chip and a control chip,
wherein one end of the at least one expansion wire is electrically connected to the first chip, and the other end of the at least one expansion wire is electrically connected to the second chip,
wherein the semiconductor apparatus further comprises at least one chip set, and each of the at least one chip set comprises at least one second chip and at least one third chip, and
wherein a plurality of chip sets are electrically connected to a plurality of first chips in a one-to-one correspondence, or one chip set is electrically connected to the plurality of first chips.