US 12,438,133 B2
Semiconductor package
Joonsung Kim, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 18, 2022, as Appl. No. 17/722,616.
Claims priority of application No. 10-2021-0108659 (KR), filed on Aug. 18, 2021.
Prior Publication US 2023/0054984 A1, Feb. 23, 2023
Int. Cl. H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/32145 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a package substrate;
a connection substrate on the package substrate and an opening that penetrates the connection substrate;
a chip stack on the package substrate and in the opening of the connection substrate;
a redistribution layer on the connection substrate and the chip stack;
an upper semiconductor chip on first redistribution pads of the redistribution layer; and
a plurality of external terminals on a bottom surface of the package substrate,
wherein the chip stack includes
a first semiconductor chip on substrate pads of the package substrate; and
a second semiconductor chip on the first semiconductor chip and on second redistribution pads of the redistribution layer,
wherein the redistribution layer includes
a first region that overlaps the upper semiconductor chip; and
a second region beside of the upper semiconductor chip,
wherein the first redistribution pads are on the first region, and
wherein the second redistribution pads are on the second region and entirely outside of the first region.