US 12,438,129 B2
Heterogeneous annealing method and device
Paul M. Enquist, Cary, NC (US); and Gaius Gillman Fountain, Jr., Youngsville, NC (US)
Assigned to Adela Semiconductor Bonding Technologies Inc., San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed on Jan. 8, 2025, as Appl. No. 19/013,905.
Application 15/639,194 is a division of application No. 14/879,800, filed on Oct. 9, 2015, granted, now 9,698,126, issued on Jul. 4, 2017.
Application 14/064,807 is a division of application No. 13/599,023, filed on Aug. 30, 2012, granted, now 8,735,219, issued on May 27, 2014.
Application 19/013,905 is a continuation of application No. 18/147,180, filed on Dec. 28, 2022, granted, now 12,199,069.
Application 18/147,180 is a continuation of application No. 16/914,169, filed on Jun. 26, 2020, granted, now 11,631,586, issued on Apr. 18, 2021.
Application 16/914,169 is a continuation of application No. 15/639,194, filed on Jun. 30, 2017, granted, now 10,777,533, issued on Sep. 15, 2020.
Application 14/879,800 is a continuation of application No. 14/064,807, filed on Oct. 28, 2013, granted, now 9,184,125.
Prior Publication US 2025/0149510 A1, May 8, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/786 (2006.01); H01L 21/20 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H10D 1/47 (2025.01); H10D 88/00 (2025.01)
CPC H01L 25/0657 (2013.01) [H01L 21/2007 (2013.01); H01L 21/6835 (2013.01); H01L 21/76898 (2013.01); H01L 23/49866 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/50 (2013.01); H10D 1/476 (2025.01); H10D 88/00 (2025.01); H01L 2221/68359 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/29155 (2013.01); H01L 2224/83053 (2013.01); H01L 2224/83201 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/0002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A bonded structure comprising:
a first semiconductor element having a first surface with a first insulating region and a first contact structure, the first semiconductor element having a thickness less than 100 microns;
a second semiconductor element having a second surface with a second insulating region and a second contact structure, wherein the first insulating region is directly bonded to the second insulating region and the first contact structure is directly bonded to the second contact structure; and
a third semiconductor element consisting of a silicon base and a bonding layer, the bonding layer of the third semiconductor element directly bonded to the first semiconductor element opposing the first surface, wherein the third semiconductor element has a thickness greater than the thickness of the first semiconductor element and wherein a difference in coefficient of thermal expansion (CTE) between the silicon base of the third semiconductor element and a base material of the second semiconductor element is less than 1.0 ppm/° C.