US 12,438,128 B2
Semiconductor device package
Shang-Ruei Wu, Kaohsiung (TW); Chien-Yuan Tseng, Kaohsiung (TW); Meng-Jen Wang, Kaohsiung (TW); Chen-Tsung Chang, Kaohsiung (TW); Chih-Fang Wang, Kaohsiung (TW); Cheng-Han Li, Kaohsiung (TW); Chien-Hao Chen, Kaohsiung (TW); An-Chi Tsao, Kaohsiung (TW); and Per-Ju Chao, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Jan. 29, 2024, as Appl. No. 18/426,124.
Application 18/426,124 is a continuation of application No. 17/493,709, filed on Oct. 4, 2021, granted, now 11,887,967.
Application 17/493,709 is a continuation of application No. 16/779,249, filed on Jan. 31, 2020, granted, now 11,139,274.
Claims priority of provisional application 62/799,701, filed on Jan. 31, 2019.
Prior Publication US 2024/0213222 A1, Jun. 27, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/02631 (2013.01); H01L 21/76838 (2013.01); H01L 23/3121 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device package, comprising:
a substrate;
a connection structure disposed over the substrate;
a package body at least partially covering the connection structure,
a first electronic component disposed under the substrate; and
a second electronic component disposed over the package body and electrically connected to the connection structure, wherein at least a part of the second electronic component is free from vertically overlapping the connection structure.