US 12,438,126 B2
Stacked integrated circuit
Dong Uk Lee, Icheon-si (KR); Kwang Myoung Rho, Icheon-si (KR); Choung Ki Song, Icheon-si (KR); Seung Han Oak, Icheon-si (KR); and Woo Yeong Cho, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 31, 2022, as Appl. No. 17/977,668.
Application 17/977,668 is a continuation in part of application No. 17/893,806, filed on Aug. 23, 2022.
Claims priority of application No. 10-2022-0062933 (KR), filed on May 23, 2022.
Prior Publication US 2023/0378135 A1, Nov. 23, 2023
Int. Cl. H01L 25/065 (2023.01); G11C 5/06 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01)
CPC H01L 25/0657 (2013.01) [G11C 5/06 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 24/02 (2013.01); H01L 24/16 (2013.01); H01L 2224/02333 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A stacked integrated circuit comprising:
a first chip comprising a first area substantially symmetrical to a second area in relation to a first rotating axis;
wherein a first through via set is connected within the first area to a first front pad set using a first connection method;
wherein a second through via set is connected within the second area to a second front pad set using a second connection method;
wherein the first through via set is disposed substantially symmetrical to the second through via set in relation to the first rotating axis; and
wherein the first front pad set is disposed substantially symmetrical to the second front pad set in relation to the first rotating axis.