	US 12,438,125 B2
	Semiconductor device with multi-directional chip guards
Nam Jae Lee, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Mar. 1, 2021, as Appl. No. 17/188,429.
Claims priority of application No. 10-2020-0109657 (KR), filed on Aug. 28, 2020.
Prior Publication US 2022/0068885 A1, Mar. 3, 2022
Int. Cl. H01L 23/62 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H10D 88/00 (2025.01)

CPC H01L 25/0657 (2013.01) [G11C 5/025 (2013.01); G11C 5/06 (2013.01); H01L 23/5386 (2013.01); H10D 88/00 (2025.01)]

16 Claims

1. A semiconductor device comprising:

a substrate with a cell region and a chip guard region, the chip guard region surrounding the cell region;

a plurality of chip guards over the chip guard region, the plurality of chip guards extending in a first direction, being spaced apart from each other in a second direction intersecting the first direction, and including a first chip guard and a second chip guard arranged closest to each other in the second direction;

a third chip guard extending over the chip guard region in the second direction; and

a fourth chip guard over the chip guard region, the fourth chip guard being spaced apart from the first, second and third chip guards in the first direction,

wherein the first chip guard includes a first end portion,

wherein the second chip guard includes a second end portion,

wherein the third chip guard includes a third end portion,

wherein the third end portion overlaps a space between the first chip guard and the second chip guard,

wherein a distance between the third chip guard and the second chip guard is different from a distance between the first chip guard and the second chip guard,

wherein the second end portion overlaps a space between the third chip guard and the fourth chip guard.

8. A semiconductor device comprising:

a substrate with a cell region and a chip guard region, the chip guard region surrounding the cell region;

a first chip guard extending over the chip guard region in a first direction;

a second chip guard extending over the chip guard region in the first direction, the second chip guard being spaced apart from the first chip guard; and

a third chip guard extending over the chip guard region in a second direction, the second direction intersecting the first direction,

wherein the first chip guard includes a first long sidewall, extending in the first direction, and a first short sidewall, extending in the second direction,

wherein the second chip guard includes a second long sidewall, extending in the first direction, and a second short sidewall, extending in the second direction,

wherein the third chip guard includes a third long sidewall, extending in the second direction, and a third short sidewall, extending in the first direction,

wherein the first short sidewall faces the third long sidewall,

wherein the third short sidewall faces the second long sidewall, and

wherein the second long sidewall continuously extends longer in the first direction than the first long sidewall.