US 12,438,124 B2
Semiconductor package with routing patch and method of fabricating the semiconductor package
Michael Kelly, Queen Creek, AZ (US); Ronald Patrick Huemoeller, Gilbert, AZ (US); and David Jon Hiner, Chandler, AZ (US)
Assigned to AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD., Singapore (SG)
Filed by Amkor Technology Singapore Holding Pte. Ltd., Singaproe (SG)
Filed on Feb. 12, 2024, as Appl. No. 18/438,638.
Application 18/438,638 is a continuation of application No. 17/706,848, filed on Mar. 29, 2022, granted, now 11,901,335.
Application 17/706,848 is a continuation of application No. 16/890,053, filed on Jun. 2, 2020, granted, now 11,289,451, issued on Mar. 29, 2022.
Application 16/890,053 is a continuation of application No. 16/127,575, filed on Sep. 11, 2018, granted, now 10,672,740, issued on Jun. 2, 2020.
Application 16/127,575 is a continuation of application No. 14/686,725, filed on Apr. 14, 2015, granted, now 10,074,630, issued on Sep. 11, 2018.
Prior Publication US 2024/0266324 A1, Aug. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 23/498 (2006.01)
CPC H01L 25/0655 (2013.01) [H01L 21/563 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 24/14 (2013.01); H01L 25/50 (2013.01); H01L 23/49816 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/92 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68363 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/29294 (2013.01); H01L 2224/2939 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83102 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/83385 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/014 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/15738 (2013.01); H01L 2924/18161 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a patch comprising a patch top side, a patch bottom side, patch signal paths, one or more patch dielectric layers, and patch lateral sides between the patch top side and the patch bottom side;
a substrate comprising a substrate top side, a substrate bottom side, substrate signal paths, and one or more substrate dielectric layers, wherein the one or more substrate dielectric layers surround the one or more patch dielectric layers and the patch lateral sides;
a first semiconductor die over the substrate top side;
a second semiconductor die over the substrate top side;
conductive interconnects along the substrate bottom side, wherein the substrate signal paths provide first signal paths between one or more of the conductive interconnects and the first semiconductor die and provide second signal paths between one or more of the conductive interconnects and the second semiconductor die; and
wherein the patch signal paths provide signal paths between the first semiconductor die and the second semiconductor die.