US 12,438,123 B2
Stacked semiconductor die architecture with multiple layers of disaggregation
Edward Burton, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 19, 2024, as Appl. No. 18/640,867.
Application 18/640,867 is a continuation of application No. 18/080,610, filed on Dec. 13, 2022, granted, now 12,015,009.
Application 18/080,610 is a continuation of application No. 16/646,974, granted, now 11,569,198, issued on Jan. 31, 2023, previously published as PCT/US2018/012170, filed on Jan. 3, 2018.
Prior Publication US 2024/0266323 A1, Aug. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/00 (2006.01); H01L 23/00 (2006.01)
CPC H01L 25/00 (2013.01) [H01L 24/16 (2013.01); H01L 2224/16145 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A stacked semiconductor architecture, comprising:
a first die and a second die; and
a layer on the first die and the second die, the layer including a first plurality of dies entirely within a footprint of the first die and a second plurality of dies within a footprint of the second die, wherein the layer electrically couples the first die to the second die with first interconnect structures, and wherein one or more second interconnect structures couple one or more of the first plurality of dies or the second plurality of dies and one or more of the first die or the second die, the one or more second interconnect structures laterally adjacent to the first interconnect structures.