US 12,438,115 B2
Power semiconductor module
Toru Masuda, Tokyo (JP); Seiichi Hayakawa, Hitachi (JP); and Yuji Takayanagi, Hitachi (JP)
Assigned to HITACHI POWER SEMICONDUCTOR DEVICE, LTD., Ibaraki (JP)
Appl. No. 17/625,815
Filed by Hitachi Power Semiconductor Device, Ltd., Hitachi (JP)
PCT Filed Apr. 6, 2020, PCT No. PCT/JP2020/015565
§ 371(c)(1), (2) Date Jan. 10, 2022,
PCT Pub. No. WO2021/014692, PCT Pub. Date Jan. 28, 2021.
Claims priority of application No. 2019-133942 (JP), filed on Jul. 19, 2019.
Prior Publication US 2022/0302075 A1, Sep. 22, 2022
Int. Cl. H01L 23/049 (2006.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01); H01L 25/07 (2006.01)
CPC H01L 24/48 (2013.01) [H01L 23/049 (2013.01); H01L 23/3735 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/072 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48139 (2013.01); H01L 2224/48175 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/30107 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A power semiconductor module comprising:
an insulated substrate;
a first and a second conductive patterns and laid out on the insulated substrate;
multiple power semiconductor chips arranged on the first and second conductive patterns, wherein each of the multiple power semiconductor chips on the first and second conductive patterns comprises a gate electrode and a source electrode;
a first wiring formed to bridge and directly connecting respective gate electrodes of the multiple power semiconductor chips;
a second wiring formed to bridge and directly connecting respective source electrodes of the multiple power semiconductor chips;
a gate control terminal electrically insulated from the first conductive pattern and situated on a casing; and
a source sense control terminal spaced from the first conductive pattern and situated on the casing,
wherein the first wiring is connected to the gate control terminal, and the second wiring is connected to the source sense control terminal,
wherein the second conductive pattern is connected with the source electrodes of multiple power semiconductor chips on the first conductive pattern by multiple bonding wires,
wherein an angle formed between the first wiring and the second wiring is 30 degrees or less and the first wiring is connected to the gate control terminal without connection to the second conductive pattern on the insulated substrate; and
the second wiring is connected to the source control terminal without connection to the first conductive pattern on the insulated substrate.