US 12,438,109 B2
Semiconductor package and manufacturing method thereof
Yan-Liang Ji, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK Inc., Hsinchu (TW)
Filed on Mar. 11, 2024, as Appl. No. 18/601,003.
Application 18/601,003 is a continuation of application No. 17/580,699, filed on Jan. 21, 2022, granted, now 11,935,852.
Claims priority of provisional application 63/172,127, filed on Apr. 8, 2021.
Prior Publication US 2024/0213194 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05094 (2013.01); H01L 2224/13026 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate;
a first insulation layer formed on the substrate and having a first through hole;
a conductive pad formed on the substrate through the first through hole;
a second insulation layer having a first surface and a second through hole, wherein the second through hole extends to the conductive pad from the first surface; and
a conductive trace having a second surface and connected to the conductive pad through the second through hole;
wherein an entirety of the first surface is in the same level, the entirety of the second surface is in the same level, and the second insulation layer comprises a plurality of layers, one of the layers has a third surface, and the third surface is in the same level.