US 12,438,103 B2
Transistor including a discontinuous barrier layer
Kyoung-Keun Lee, Cary, NC (US); and Jia Guo, Apex, NC (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Apr. 29, 2022, as Appl. No. 17/733,939.
Prior Publication US 2023/0352424 A1, Nov. 2, 2023
Int. Cl. H01L 21/8238 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H10D 30/47 (2025.01); H10D 64/00 (2025.01)
CPC H01L 23/564 (2013.01) [H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H10D 30/475 (2025.01); H10D 64/111 (2025.01)] 43 Claims
OG exemplary drawing
 
1. A transistor comprising:
a first passivation layer on a semiconductor layer of the transistor between a source contact and a drain contact, the first passivation layer comprising a portion having a topological change; and
a discontinuous barrier layer on the portion of the first passivation layer having the topological change, wherein the discontinuous barrier layer is configured to reduce ingress of moisture in the portion of the first passivation layer.