US 12,438,102 B2
Hermetic barrier surrounding a plurality of dies
Mohammad Enamul Kabir, Portland, OR (US); Keith Zawadzki, Portland, OR (US); Shakul Tandon, Hillsboro, OR (US); Christopher M. Pelto, Beaverton, OR (US); John Kevin Taylor, Portland, OR (US); and Babita Dhayal, Aloha, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2021, as Appl. No. 17/557,565.
Prior Publication US 2023/0197638 A1, Jun. 22, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/52 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/564 (2013.01) [H01L 21/52 (2013.01); H01L 25/0655 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a silicon substrate;
a first die on a side of the silicon substrate;
a second die on the side of the silicon substrate;
one or more electrical connections electrically coupling the first die and the second die; and
a barrier completely laterally surrounding the first die, the second die, and the one or more electrical connections, wherein the barrier extends from the silicon substrate to a top of the first die or the second die, and wherein the barrier is a hermetic barrier.