US 12,438,100 B2
Three-dimensional memory device with multiple types of support pillar structures and method of forming the same
Katsuo Yamada, Yokkaichi (JP); Kakeru Tamai, Yokkaichi (JP); Akira Iwasaki, Yokkaichi (JP); Akira Fukunaga, Yokkaichi (JP); and Koichi Matsuno, Fremont, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Jun. 13, 2022, as Appl. No. 17/806,592.
Application 17/806,592 is a continuation in part of application No. 17/244,311, filed on Apr. 29, 2021, granted, now 12,096,632.
Prior Publication US 2022/0352093 A1, Nov. 3, 2022
Int. Cl. H01L 23/00 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H10B 51/20 (2023.01)
CPC H01L 23/562 (2013.01) [H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 51/20 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
memory opening fill structures located within a respective memory opening vertically extending through the alternating stack in a memory array region, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective memory film that contacts each layer within the alternating stack; and
support pillar structures vertically extending through the alternating stack, wherein each of the support pillar structures comprises a respective dummy vertical semiconductor channel, a respective dummy memory film, and at least one respective dielectric spacer material portion laterally surrounding the respective dummy memory film and interposed between the electrically conductive layers and the respective dummy memory film;
wherein:
the alternating stack is located over a substrate;
each layer within the alternating stack is present within the memory array region;
the alternating stack comprises stepped surfaces in a staircase region in which the electrically conductive layers have variable lateral extents with a vertical distance from the substrate;
a retro-stepped dielectric material portion is located in the staircase region and overlies the stepped surfaces of the alternating stack; and
the support pillar structures are located in the staircase region and vertically extend through the retro-stepped dielectric material portion and through a respective subset of the alternating stack; and
further comprising at least one feature selected from:
(a) each dielectric spacer material portion of the support pillar structures has an inner sidewall contacting a respective memory film and an outer sidewall contacting a respective subset of layers within the alternating stack and the retro-stepped dielectric material portion; and the inner sidewall has a greater taper angle relative to a vertical direction than the outer sidewall for each of the dielectric spacer material portions; or
(b) each dielectric spacer material portion of the support pillar structures has a variable lateral spacing between a respective inner sidewall and a respective outer sidewall that decreases with a vertical distance from the substrate; or
(c) each of the memory opening fill structures comprises a respective dielectric core that is laterally surrounded by the respective vertical semiconductor channel; and each of the support pillar structures comprises a respective dummy dielectric core that is laterally surrounded by the respective dummy vertical semiconductor channel, wherein a taper angle of the respective dummy dielectric core relative to a vertical direction is greater than a taper angle of the respective dielectric core relative to the vertical direction; or
(d) each of the dummy memory films has a conical bottom tip that is embedded within a respective one of the dielectric spacer material portions; and each of the memory films has an annular bottom surface; or
(e) at least one of the support pillar structures comprises a respective dielectric spacer material portion having a topmost surface located below a horizontal plane including a top surface of the retro-stepped dielectric material portion and a sidewall contacting a cylindrical surface segment of the retro-stepped dielectric material portion.