US 12,438,098 B2
Packaging structure and fabrication method thereof
Yujuan Tao, Nantong (CN)
Assigned to NANTONG TONGFU MICROELECTRONICS CO., LTD., Nantong (CN); and TONGFU MICROELECTRONICS CO., LTD., Nantong (CN)
Appl. No. 17/629,672
Filed by NANTONG TONGFU MICROELECTRONICS CO., LTD., Nantong (CN); and TONGFU MICROELECTRONICS CO., LTD., Nantong (CN)
PCT Filed Jul. 17, 2020, PCT No. PCT/CN2020/102762
§ 371(c)(1), (2) Date Jan. 24, 2022,
PCT Pub. No. WO2021/017897, PCT Pub. Date Feb. 4, 2021.
Claims priority of application No. 201910681485.8 (CN), filed on Jul. 26, 2019; application No. 201910681489.6 (CN), filed on Jul. 26, 2019; application No. 201910681772.9 (CN), filed on Jul. 26, 2019; and application No. 201910681773.3 (CN), filed on Jul. 26, 2019.
Prior Publication US 2022/0285287 A1, Sep. 8, 2022
Int. Cl. H01L 23/552 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/552 (2013.01) [H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3135 (2013.01); H01L 24/03 (2013.01); H01L 24/96 (2013.01); H01L 2224/02311 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A fabrication method for a packaging structure, comprising:
providing semiconductor chips, wherein each semiconductor chip includes a functional surface, a non-functional surface opposite to the functional surface, soldering pads on the functional surface, a metal bump on each soldering pad;
forming a bottom shielding layer on the functional surface of each semiconductor chip to cover a whole functional surface of the semiconductor chip;
forming a first plastic encapsulation layer on functional surfaces of the semiconductor chips and covering metal bumps of the semiconductor chips;
providing a carrier plate;
adhering the first plastic encapsulation layer on the functional surfaces of the semiconductor chips to the carrier plate;
forming a first shielding layer covering non-functional surfaces and sidewalls of the semiconductor chips, wherein the first shielding layer is formed to connect to surrounding edges of the bottom shielding layer;
forming a second shielding layer on the first shielding layer;
forming a second plastic encapsulation layer on the second shielding layer and on a portion of the carrier plate between semiconductor chips;
peeling off the carrier plate to form a pre-packaging plate, wherein a backside of the pre-packaging plate exposes the first plastic encapsulation layer;
removing a portion of the first plastic encapsulation layer to expose metal bumps; and
forming an external contact structure on the backside of the pre-packaging plate and connected to each metal bump, wherein
the surrounding edges of the bottom shielding layer are flush with surrounding sidewalls of the semiconductor chips, and
the soldering pads penetrate through the bottom shielding layer and are isolated from the bottom shielding layer by isolation layers.