US 12,438,095 B1
Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates
Syrus Ziai, Los Altos, CA (US); and Ramin Farjadrad, Los Altos, CA (US)
Assigned to Eliyan Corp., Santa Clara, CA (US)
Filed by Eliyan Corporation, Los Altos, CA (US)
Filed on May 5, 2022, as Appl. No. 17/737,966.
Claims priority of provisional application 63/184,842, filed on May 6, 2021.
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5386 (2013.01) [H01L 23/145 (2013.01); H01L 23/5382 (2013.01); H01L 24/16 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 23/5381 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chiplet-based multi-chip module (MCM) to couple to a base substrate, the chiplet-based MCM comprising:
a package substrate that is separate from the base substrate;
a first integrated circuit (IC) chiplet coupled to the package substrate and comprising a first memory interface, the first memory interface to transmit memory access information sufficient to carry out a memory access operation; and
a second IC chiplet comprising a first memory chiplet coupled to the package substrate and comprising:
at least one dynamic random access memory (DRAM) die comprising a memory space;
a first port to receive the memory access information to access the memory space, the memory access information issued from the first memory interface of the first IC chiplet;
a second port to communicate with a third IC chiplet;
a third port to communicate with the memory space; and
first network-on-chip (NoC) circuitry to control a transfer of the memory access information from the first port to the second port or the third port via a network-based protocol.