US 12,438,092 B2
Semiconductor device having contact plug connected to gate structure on PMOS region
Shih-Cheng Chen, Tainan (TW); Li-Hsuan Ho, Kaohsiung (TW); Tsuo-Wen Lu, Kaohsiung (TW); Shih-Hao Liang, Tainan (TW); Tsung-Hsun Wu, Kaohsiung (TW); Po-Jen Chuang, Kaohsiung (TW); and Chi-Mao Hsu, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jul. 4, 2024, as Appl. No. 18/764,355.
Application 18/764,355 is a continuation of application No. 18/226,784, filed on Jul. 27, 2023, granted, now 12,057,401.
Application 18/226,784 is a continuation of application No. 17/493,852, filed on Oct. 5, 2021, granted, now 11,756,888, issued on Sep. 12, 2023.
Application 17/493,852 is a continuation of application No. 16/695,028, filed on Nov. 25, 2019, granted, now 11,171,091, issued on Nov. 9, 2021.
Claims priority of application No. 201911033932.5 (CN), filed on Oct. 28, 2019.
Prior Publication US 2024/0363539 A1, Oct. 31, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/535 (2006.01); H01L 21/28 (2025.01); H01L 23/528 (2006.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01)
CPC H01L 23/535 (2013.01) [H01L 21/28088 (2013.01); H01L 23/528 (2013.01); H10D 64/017 (2025.01); H10D 64/667 (2025.01); H10D 84/0179 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 1 Claim
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate having a NMOS region and a PMOS region;
a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate;
a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region;
a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region;
a first contact plug landing on the second source/drain region adjacent to one side of the metal gate;
a second contact plug landing on the second source/drain region adjacent to another side of the metal gate;
a third contact plug landing directly on a portion of the metal gate on the PMOS region not between the first source/drain region and the second source/drain region, away from a boundary separating the NMOS region and the PMOS region, and near an end of the metal gate on the PMOS region; and
a fourth contact plug landing on the first source/drain region adjacent to one side of the metal gate.