US 12,438,090 B2
Three-dimensional memory device and methods for forming the same
Mingkang Zhang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Sep. 29, 2021, as Appl. No. 17/488,766.
Application 17/488,766 is a continuation of application No. PCT/CN2021/115757, filed on Aug. 31, 2021.
Prior Publication US 2023/0061992 A1, Mar. 2, 2023
Int. Cl. H01L 25/18 (2023.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/535 (2013.01) [H01L 21/76886 (2013.01); H01L 21/76895 (2013.01); H01L 23/53271 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising:
an array of NAND memory strings,
a first contact structure extending vertically at a lateral side of the array of NAND memory strings,
a semiconductor layer having a lower surface in contact with source ends of the array of NAND memory strings,
a non-conductive layer having an upper surface aligned with an upper surface of the semiconductor layer along a lateral plane,
a first insulating layer in contact with the upper surface of the non-conductive layer and the upper surface of the semiconductor layer,
a plurality of second contact structures in the non-conductive layer and the first insulating layer, one of the second contact structures being in contact with the first contact structure, wherein the non-conductive layer electrically insulates the second contact structures from each other and insulates the second contact structures from the semiconductor layer, and
a third contact structure in the first insulating layer and in direct contact with the upper surface of the semiconductor layer; and
a second semiconductor structure, bonded with the first semiconductor structure, comprising a transistor.