US 12,438,088 B2
Composite interconnect semiconductor device structure
Tse-Yao Huang, Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Aug. 5, 2022, as Appl. No. 17/881,843.
Prior Publication US 2024/0047358 A1, Feb. 8, 2024
Int. Cl. H01L 23/532 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/3205 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/53271 (2013.01) [H01L 21/31111 (2013.01); H01L 21/31155 (2013.01); H01L 21/32055 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01)] 17 Claims
OG exemplary drawing
 
11. A semiconductor device structure, comprising:
a first lower semiconductor structure disposed on a top surface of a semiconductor substrate, wherein the first lower semiconductor structure has a first sidewall and a second sidewall opposite to the first sidewall;
a first upper semiconductor structure covering a top surface and the first sidewall of the first lower semiconductor structure, wherein the first lower semiconductor structure and the first upper semiconductor structure comprise different materials;
a first oxide portion disposed on the top surface of the semiconductor substrate and extending along the second sidewall of the first lower semiconductor structure; and
a dielectric layer disposed over the first oxide portion, wherein the first oxide portion separates the dielectric layer from the semiconductor substrate, wherein the semiconductor substrate is separated from the dielectric layer by the first oxide portion;
wherein a bottom surface of the first upper semiconductor structure is higher than a bottom surface of the first lower semiconductor structure, wherein the bottom surface of the first lower semiconductor structure is in direct contact with the top surface of the semiconductor structure.