US 12,438,083 B2
Assemblies having conductive interconnects which are laterally and vertically offset relative to one another
Raju Ahmed, Boise, ID (US); Radhakrishna Kotti, Boise, ID (US); David A. Kewley, Boise, ID (US); and Dave Pratt, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 1, 2024, as Appl. No. 18/652,079.
Application 18/652,079 is a division of application No. 17/947,038, filed on Sep. 16, 2022, granted, now 12,014,983.
Application 17/947,038 is a continuation of application No. 16/925,767, filed on Jul. 10, 2020, granted, now 11,482,492, issued on Oct. 25, 2022.
Prior Publication US 2024/0282702 A1, Aug. 22, 2024
Int. Cl. H01L 23/528 (2006.01); H01L 23/522 (2006.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC H01L 23/528 (2013.01) [H01L 23/5226 (2013.01); H10B 61/00 (2023.02); H10B 63/84 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A method of forming an integrated assembly, the method comprising:
providing a base comprising a first circuitry;
forming memory arrays over the base and each of the memory arrays comprising a sense/access line, the memory arrays being vertically spaced from one another by gaps, the gaps alternating in a vertical direction between first gaps and second gaps, a gap between the base and a bottommost of the memory arrays being one of the first gaps; and
forming conductive paths overlapping among themselves and extending from the sense/access lines to the first circuitry, the conductive paths comprising:
first conductive interconnects within the first gaps; and
second conductive interconnects within the second gaps;
the first and second conductive interconnects being laterally spaced relative to one another.