US 12,438,081 B2
Semiconductor structure having dielectric liner and method of manufacturing the same
Feng-Wen Hsu, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Apr. 6, 2023, as Appl. No. 18/131,462.
Prior Publication US 2024/0339398 A1, Oct. 10, 2024
Int. Cl. H01L 23/528 (2006.01)
CPC H01L 23/528 (2013.01) 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a first bit line structure, disposed over the substrate, comprising a first conductive layer formed on and in contact with the substrate, a second conductive layer disposed over and in contact with the first conductive layer, and a first dielectric layer disposed over and in contact with the second conductive layer;
a second bit line structure, disposed over the substrate, comprising a second dielectric layer formed on and in contact with the substrate, a third conductive layer disposed over and in contact with the second dielectric layer, and a third dielectric layer disposed over and in contact with the third conductive layer;
a polysilicon layer, disposed over and in contact with the substrate and surrounded by the first bit line structure and the second bit line structure;
a dielectric liner, surrounding at least a portion of the polysilicon layer; and
a landing pad, disposed over the polysilicon layer, the dielectric liner and the second bit line structure;
wherein a width of the first bit structure is equal to a width of the second bit structure, such that the first conductive layer, the second conductive layer, the first dielectric layer, the second dielectric layer, the third conductive layer, and the third dielectric layer are equal in width.