US 12,438,080 B2
And process for a precision resistor
Sagar Suthram, Portland, OR (US); Seung-June Choi, Portland, OR (US); Vishal Javvaji, Hillsboro, OR (US); Soumya Kar, Hillsboro, OR (US); Ahmed Esmail, Hillsboro, OR (US); and Gokul Malyavanatham, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 28, 2018, as Appl. No. 16/147,112.
Prior Publication US 2020/0105669 A1, Apr. 2, 2020
Int. Cl. H01L 23/522 (2006.01); H01L 23/66 (2006.01); H10D 1/47 (2025.01); H10D 86/85 (2025.01)
CPC H01L 23/5228 (2013.01) [H01L 23/5226 (2013.01); H01L 23/66 (2013.01); H10D 1/47 (2025.01); H10D 86/85 (2025.01); H01L 2223/6672 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
back end layers, including:
a first metallization layer in a first dielectric layer;
a second metallization layer;
an etch stop layer over the first metallization layer and the first dielectric layer; and
a thin film resistor over the etch stop layer and between the first metallization layer and the second metallization layer, wherein the second metallization layer includes a plurality of contacts to the thin film resistor and a conductive line over and coupled to one of the plurality of contacts, the conductive line extending laterally beyond the thin film resistor, wherein the plurality of contacts is on the thin film resistor but does not extend entirely through the thin film resistor, and wherein the thin film resistor vertically overlaps and extends laterally beyond outermost laterally opposite sidewalls of an uppermost portion of a metal interconnect of the first metallization layer immediately below the thin film resistor; and
front end layers, the front end layers comprising a plurality of gate structures, wherein the thin film resistor is vertically overlapping with the plurality of gate structures.