US 12,438,076 B2
Memory array having an intervening material between adjacent memory blocks with an elongated seam therein
Yi Hu, Boise, ID (US); Harsh Narendrakumar Jain, Boise, ID (US); and Matthew J. King, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jul. 26, 2021, as Appl. No. 17/385,299.
Application 17/385,299 is a division of application No. 16/664,618, filed on Oct. 25, 2019, granted, now 11,101,210.
Prior Publication US 2021/0351127 A1, Nov. 11, 2021
Int. Cl. H10B 41/27 (2023.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H01L 23/5226 (2013.01) [H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel material strings of memory cells extending through the insulative tiers and the conductive tiers; and
intervening material laterally-between and longitudinally-along immediately laterally-adjacent of the memory blocks, the intervening material comprising longitudinally-alternating first and second regions individually having a vertically-elongated seam therein, the vertically-elongated seam in the first regions having a higher top than in the second regions, seam tops in the second regions are elevationally-coincident with a bottom of the uppermost conductive tier.
 
8. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel material strings of memory cells extending through the insulative tiers and the conductive tiers; and
intervening material laterally-between and longitudinally-along immediately laterally-adjacent of the memory blocks, the intervening material comprising a vertically-elongated seam therein, wherein a seam top of the vertically-elongated seam between insulating bridges is higher than a seam top of the vertically-elongated seam that is directly under an insulating bridge.
 
9. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel material strings of memory cells extending through the insulative tiers and the conductive tiers;
intervening material laterally-between and longitudinally-along immediately laterally-adjacent of the memory blocks, the intervening material comprising a vertically-elongated seam therein that has a top that is elevationally coincident with or below an uppermost of the insulative tiers; and
insulating bridges within the stack extending laterally between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks, the insulating bridges being spaced above the seam top, the insulating bridges individually having a planar top that is co-planar with a planar top of the uppermost of the insulative tiers.
 
10. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel material strings of memory cells extending through the insulative tiers and the conductive tiers; and
intervening material laterally-between and longitudinally-along immediately laterally-adjacent of the memory blocks, the intervening material comprising longitudinally-alternating first and second regions individually having a vertically-elongated seam therein, the vertically-elongated seam in the first regions having a higher top than in the second regions, seam tops in the second regions being below a bottom of an uppermost of the conductive tiers, wherein the seam tops in the second regions are in a lowest half of the stack.
 
11. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel material strings of memory cells extending through the insulative tiers and the conductive tiers; and
intervening material laterally-between and longitudinally-along immediately laterally-adjacent of the memory blocks, the intervening material comprising longitudinally-alternating first and second regions individually having a vertically-elongated seam therein, the vertically-elongated seam in the first regions having a higher top than in the second regions, seam tops in the second regions being elevationally-coincident with or below a bottom of an uppermost of the conductive tiers, the vertically-elongated seam in the first and second regions comprises at least one void space, and the vertically-elongated seam in the first and second regions comprises multiple vertically spaced void spaces.