US 12,438,072 B2
Multilayer package substrate with stress buffer
Guangxu Li, Allen, TX (US); Yiqi Tang, Allen, TX (US); and Rajen Manicon Murugan, Dallas, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Oct. 9, 2023, as Appl. No. 18/482,944.
Application 18/482,944 is a continuation of application No. 17/233,110, filed on Apr. 16, 2021, granted, now 11,784,113.
Claims priority of provisional application 63/011,295, filed on Apr. 17, 2020.
Prior Publication US 2024/0112997 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49811 (2013.01) [H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/1357 (2013.01); H01L 2224/16227 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A multilayer package substrate, comprising:
a top layer including a top dielectric layer and a top metal layer including top side contact pads providing at least a top portion for a plurality of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads, the top dielectric layer together with the bottom dielectric layer providing electrical isolation between the plurality of pins;
wherein the top side contact pads comprise an integrated circuit (IC) bondable portion that is configured for an electrically conductive material interconnect to provide a connection to bonding features on bond pads of an IC die; and
wherein at least a first pin of the plurality of pins includes at least one bump stress reduction structure (BSRS).