| CPC H01L 23/49811 (2013.01) [H01L 21/4842 (2013.01); H01L 21/4853 (2013.01); H01L 23/535 (2013.01)] | 3 Claims |

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1. A semiconductor device comprising:
an insulating substrate having a wiring pattern in a surface layer thereof; and
a terminal electrode having a bag-shaped internal space with a terminal electrode tip aperture, wherein
the terminal electrode is grounded in a freestanding state by mating with the wiring pattern.
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