US 12,438,067 B2
Flip chip self-alignment features for substrate and leadframe applications and method of manufacturing the flip chip self-alignment features
Marc Alan Mangrum, Manchaca, TX (US)
Assigned to Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed by Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed on May 22, 2023, as Appl. No. 18/200,130.
Application 18/200,130 is a continuation of application No. 17/113,498, filed on Dec. 7, 2020, granted, now 11,658,099.
Application 17/113,498 is a continuation of application No. 16/042,566, filed on Jul. 23, 2018, granted, now 10,861,776, issued on Dec. 8, 2020.
Application 16/042,566 is a continuation of application No. 14/264,027, filed on Apr. 28, 2014, granted, now 10,032,699, issued on Jul. 24, 2018.
Prior Publication US 2023/0369182 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/544 (2006.01)
CPC H01L 23/49541 (2013.01) [H01L 21/4825 (2013.01); H01L 23/49548 (2013.01); H01L 23/544 (2013.01); H01L 24/81 (2013.01); H01L 21/4828 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/81143 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81385 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/14 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of manufacturing an electronic device, the method comprising:
placing a plurality of bumps of an electronic component on a top side of a plurality of bond fingers of a metal leadframe, wherein:
each of the plurality of bumps comprises a metal pillar and a solder cap,
each of at least two of the plurality of bond fingers comprises a curved sidewall recessed self-alignment feature, and
each of the curved sidewall recessed self-alignment feature comprises a maximum width at a top end positioned toward the electronic component and a minimum width at a bottom end positioned away from the electronic component; and
performing a mass reflow process, thereby melting the solder cap of each of the plurality of bumps, wherein:
at least one of the plurality of bumps is configured to be pulled into a respective one of the curved sidewall recessed self-alignment feature to align the plurality of bumps to the plurality of bond fingers, and
a continuous bond extending entirely about a circumference of the at least one of the plurality of bumps is formed between the at least one of the plurality of bumps and the respective one of the curved sidewall recessed self-alignment feature.