US 12,438,065 B2
Fully molded semiconductor structure with through silicon via (TSV) vertical interconnects
Robin Davis, Vancouver, WA (US); Timothy L. Olson, Phoenix, AZ (US); Craig Bishop, Scottsdale, AZ (US); and Clifford Sandstrom, Richfield, MN (US)
Assigned to Deca Technologies USA, Inc., Tempe, AZ (US)
Filed by Deca Technologies USA, Inc., Tempe, AZ (US)
Filed on Aug. 2, 2023, as Appl. No. 18/364,314.
Application 18/364,314 is a division of application No. 17/842,491, filed on Jun. 16, 2022, granted, now 11,728,248.
Claims priority of provisional application 63/217,640, filed on Jul. 1, 2021.
Prior Publication US 2023/0378029 A1, Nov. 23, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01)
CPC H01L 23/481 (2013.01) [H01L 21/565 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/16 (2013.01); H01L 25/0652 (2013.01); H01L 23/49811 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 24/96 (2013.01); H01L 25/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2924/182 (2013.01); H01L 2924/37001 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A method of making a component package, comprising:
disposing a large semiconductor die face up over a temporary carrier, the large semiconductor die comprising conductive interconnects over an active surface of the large semiconductor die;
disposing a first encapsulant around four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects;
planarizing the first encapsulant over an active surface of the large semiconductor die to create a planar surface comprising exposed ends of the conductive interconnects and exposed first encapsulant;
forming a first build-up interconnect structure over the large semiconductor die and over the first encapsulant in a periphery of the large semiconductor die;
forming vertical conductive interconnects over the first build-up interconnect structure and around an embedded device mount site;
disposing an embedded device over the embedded device mount site, wherein the embedded device comprises through silicon vias (TSVs) and is disposed completely within a footprint of the large semiconductor die;
disposing a second encapsulant over the first build-up interconnect structure, and around at least five sides of the embedded device;
planarizing the second encapsulant, the embedded device, the TSVs, and the vertical conductive interconnects to form a planar surface; and
forming a second build-up structure disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.