US 12,438,064 B2
Semiconductor package with bonding interface
Minki Kim, Suwon-si (KR); Seungduk Baek, Hwaseong-si (KR); Soojeoung Park, Hwaseong-si (KR); and Hyuekjae Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 30, 2022, as Appl. No. 17/854,659.
Claims priority of application No. 10-2021-0135183 (KR), filed on Oct. 12, 2021.
Prior Publication US 2023/0113465 A1, Apr. 13, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/481 (2013.01) [H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 24/16 (2013.01); H01L 2224/05007 (2013.01); H01L 2224/05009 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/05078 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05084 (2013.01); H01L 2224/05087 (2013.01); H01L 2224/05187 (2013.01); H01L 2224/05547 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05578 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05687 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08059 (2013.01); H01L 2224/08121 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/80097 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/80948 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15331 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first semiconductor chip comprising a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer in a vertical direction, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer on a side surface of the first bonding pad; and
a second semiconductor chip on the first semiconductor chip and comprising a second semiconductor layer, a second bonding pad below the second semiconductor layer and bonded to the first bonding pad, and a second insulating bonding layer on a side surface of the second bonding pad and bonded to the first insulating bonding layer,
wherein the first insulating bonding layer comprises a first insulating material,
the second insulating bonding layer comprises a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer,
the first insulating layer comprises a second insulating material, different from the first insulating material,
the second insulating layer comprises a third insulating material, different from the second insulating material,
wherein the first bonding pad and the second bonding pad bonded to each other to form a portion of the bonding interface have an asymmetrical structure in which at least one of widths and thicknesses thereof are different.