| CPC H01L 23/16 (2013.01) [H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01)] | 20 Claims |
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1. A semiconductor package comprising:
a first semiconductor chip comprising a first semiconductor substrate having a first active layer, at least one first via electrode connected to the first active layer and penetrating through at least a portion of the first semiconductor substrate in a vertical direction, at least one first lower chip pad on a bottom surface of the first semiconductor substrate, and at least one first upper chip pad on a top surface of the first semiconductor substrate and connected to the at least one first via electrode;
a lower dam structure on an edge of the top surface of the first semiconductor substrate;
a second semiconductor chip mounted to the first semiconductor chip, the second semiconductor chip comprising a second semiconductor substrate having a second active layer, and at least one second lower chip pad on a bottom surface of the second semiconductor substrate;
an upper dam structure on an edge of the bottom surface of the second semiconductor substrate;
at least one chip connecting terminal electrically connecting the at least one first upper chip pad of the first semiconductor chip and the at least one second lower chip pad of the second semiconductor chip; and
an adhesive layer between the first semiconductor chip and the second semiconductor chip, the adhesive layer surrounding the at least one first upper chip pad, the at least one second lower chip pad, and the at least one chip connecting terminal,
wherein the adhesive layer is included in a space between an upper surface of the lower dam structure and a lower surface of the upper dam structure.
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