| CPC H01L 23/047 (2013.01) [H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/16 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48175 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1715 (2013.01)] | 14 Claims |
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1. A semiconductor device comprising:
a base substrate that is conductive and has a mountable area;
a semiconductor chip mounted on the mountable area and having a signal pad;
a frame surrounding the mountable area in a plan view, the frame being mounted on the base substrate, and including an inner first upper surface, an outer second upper surface, and a step in the plan view, the inner first upper surface being provided between the mountable area and the outer second upper surface in the plan view, the inner first upper surface being higher than the mountable area and lower than the outer second upper surface in a normal direction, the step being formed between the inner first upper surface and the outer second upper surface, and the inner first upper surface having a first conductor pattern that is electrically grounded and electrically connected to the base substrate;
a signal terminal mounted on the outer second upper surface of the frame;
a capacitive component mounted on the first conductor pattern such that the capacitive component is interposed both physically and electrically between the signal pad and the signal terminal and provided out of the mountable area in the plan view;
a first bonding wire configured to electrically connect the signal pad and an upper surface of the capacitive component;
a second bonding wire configured to electrically connect the upper surface of the capacitive component and the signal terminal; and
a cover joined to the outer second upper surface of the frame, and sealing the semiconductor chip in an inner space.
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