US 12,438,054 B2
Semiconductor device including a macro pattern structure for monitoring of line widths
Jungkee Choi, Hwaseong-si (KR); Sangwoo Park, Suwon-si (KR); and Woonhyuk Choi, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 4, 2023, as Appl. No. 18/149,974.
Claims priority of application No. 10-2022-0014738 (KR), filed on Feb. 4, 2022.
Prior Publication US 2023/0253267 A1, Aug. 10, 2023
Int. Cl. H01L 21/66 (2006.01)
CPC H01L 22/12 (2013.01) [H01L 22/34 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a metal pattern within a device region of a substrate; and
a macro pattern structure within a scribe lane region of the substrate,
wherein the macro pattern structure includes a plurality of types of macro patterns,
wherein each type of macro pattern of the plurality of types of macro patterns includes a first pattern and a second pattern adjacent to the first pattern,
wherein the first pattern and the second pattern each include at least one conductive line extending in a first direction that is parallel to a surface of the substrate,
wherein the first pattern and the second pattern are arranged alternately in a second direction perpendicular to the first direction and parallel to the surface of the substrate, and
wherein the first pattern and the second pattern are different from one another.