US 12,438,050 B2
Electronic device fabrication using area-selective deposition
Zachary J. Devereaux, Webberville, MI (US); Bhaskar Jyoti Bhuyan, Santa Clara, CA (US); Thomas Joseph Knisley, Livonia, MI (US); Zeqing Shen, San Jose, CA (US); Susmit Singha Roy, Campbell, CA (US); Mark J. Saly, Santa Clara, CA (US); and Abhijit Basu Mallick, Fremont, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Feb. 14, 2023, as Appl. No. 18/109,365.
Prior Publication US 2024/0282632 A1, Aug. 22, 2024
Int. Cl. H01L 21/768 (2006.01); C23C 16/04 (2006.01); C23C 16/32 (2006.01); C23C 16/40 (2006.01); C23C 16/455 (2006.01); H01L 21/02 (2006.01)
CPC H01L 21/76897 (2013.01) [C23C 16/042 (2013.01); C23C 16/32 (2013.01); C23C 16/402 (2013.01); C23C 16/45527 (2013.01); H01L 21/02126 (2013.01); H01L 21/02164 (2013.01); H01L 21/0228 (2013.01); H01L 21/02304 (2013.01); H01L 21/76802 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlevel dielectric (ILD) layer;
selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer; and
selectively forming at least one supplemental dielectric layer using the at least one catalyst layer, wherein the at least one catalyst layer induces formation of the at least one supplemental dielectric layer, and wherein the at least one supplemental dielectric layer comprises a dielectric material having a dielectric constant of less than or equal to about 4.