US 12,438,049 B2
Methods for reducing contact depth variation in semiconductor fabrication
Yun Lee, Taipei County (TW); Chen-Ming Lee, Taoyuan County (TW); Fu-Kai Yang, Hsinchu (TW); Yi-Jyun Huang, New Taipei (TW); Sheng-Hsiung Wang, Hsinchu County (TW); and Mei-Yun Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 8, 2022, as Appl. No. 17/818,289.
Application 17/818,289 is a division of application No. 16/688,071, filed on Nov. 19, 2019, granted, now 11,495,494.
Application 16/688,071 is a division of application No. 16/201,282, filed on Nov. 27, 2018, granted, now 11,062,945, issued on Jul. 13, 2021.
Application 16/201,282 is a division of application No. 15/690,709, filed on Aug. 30, 2017, granted, now 10,685,880, issued on Jun. 16, 2020.
Prior Publication US 2022/0376043 A1, Nov. 24, 2022
Int. Cl. H10D 30/62 (2025.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 84/83 (2025.01)
CPC H01L 21/76895 (2013.01) [H01L 21/0217 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/76805 (2013.01); H01L 21/76826 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 23/535 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 62/115 (2025.01); H10D 84/834 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a substrate;
an isolation feature disposed over the substrate;
a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature;
a gate structure disposed directly over the isolation feature;
a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure;
a first etch stop layer disposed between the first dielectric layer and the isolation feature;
a second dielectric layer disposed directly above the first dielectric layer;
a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer, wherein the first etch stop layer is also disposed between the gate structure and the second etch stop layer; and
a first conductive feature directly above the isolation feature and penetrating through the second dielectric layer and the second etch stop layer to directly contact a top surface of the first dielectric layer.