US 12,438,046 B2
Dual redistribution layer structure
Mukta G. Farooq, Hopewell Junction, NY (US); and James J. Kelly, Schenectady, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Apr. 22, 2022, as Appl. No. 17/727,030.
Application 17/727,030 is a division of application No. 16/518,166, filed on Jul. 22, 2019, granted, now 11,315,831.
Prior Publication US 2022/0246472 A1, Aug. 4, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 21/76877 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76873 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for fabricating a dual redistribution layer (RDL) interposer structure, comprising:
etching a semiconductor substrate to expose natural crystallographic planes to form trenches;
depositing conductive material within the trenches of the etched semiconductor substrate to form vias for an interposer structure;
placing back end of line (BEOL) inter-chip wiring on a top side of the interposer structure using a first RDL;
etching a backside of the semiconductor substrate to expose peaks of the vias;
forming a diffusion barrier layer on the peaks of the vias and the backside of the semiconductor substrate;
exposing the vias on a back side of the interposer structure by planarizing until a horizonal portion of the diffusion barrier layer is reached; and
forming at least one power RDL in contact with the vias on the back side of the interposer structure using conductive lines in a dielectric layer.